High power amplifiers (HPAs) for third-generation (3G) wireless communication systems and wireless local area network (WLAN) like IEEE811.x or IEEE816.x need high linearity at the HPA output, to achieve a high adjacent channel leakage ratio (ACLR) and low error vector magnitude (EVM). In addition, high efficiency is desirable. However, when operating with high efficiency, HPAs are the most non-linear. Digital predistortion (DPD) is an efficient cost-effective means of compensating for HPA nonlinearity and retaining high efficiency.
The DPD reference design (see non-patent document 1) implements an adaptive lookup table (LUT) and applies correction values from the LUT to the incoming stream of samples. It also compares the measured output with the input, and uses this measurement to update the LUT, making the system adaptive.
For 3G and WLAN systems the DPD reference design can operate on up to four universal mobile telecommunication systems (UMTS) channels and correct 3rd and 5th order intermodulation products.
DPD is commonly used to linearize HPAs. Ideal HPAs are perfectly linear. Denoting input and output amplitude and a coefficient by VIN, VOUT and k, respectively, their response can be described with the following equation (see line 101 in FIG. 1).VOUT=k·VIN  (1)
However, real HPAs as used in wireless system exhibit some nonlinearities and eventually reach saturation. This nonlinearity can be expressed as follows by adding the term fNL into the equation (1), where fNL is used to describe the nonlinearity (see curve 102 in FIG. 1).VOUT=fNL·k·VIN  (2)
The nonlinearity adversely affects the overall performance of a wireless system. It causes in-band distortion, which degrades the performance of the receiver, and out-of-band distortion, which degrades the performance of receivers in adjacent channels.
The task of the predistorter is to add predistortion before the power amplifier, which is exactly the inverse of the distortion caused by the power amplifier i.e. equals fNL−1. When combining the predistorter with the power amplifier, the terms fNL and fNL−1 cancel out, and the overall system can be described by the ideal HPA equation (1).
The nonlinearity of the HPA is affected by ageing and changes in the operating environment, in particular the temperature. For this reason, the nonlinearity changes over time, and the solution should be made adaptive such that the predistorter tracks the changes in behavior of HPA.
FIG. 2 describes the basic algorithm implemented in the reference design. The incoming complex sample S(t) at time t has correction factor h applied from LUT 208 at mixer 201 and then sent to radio frequency (RF) I-Q modulator 203 through digital-analog converter (DAC) 202. The address for the LUT 208 is derived from the input power by address calculator 205. The correction factor h is complex so the LUT 208 must contain two values for each location—the real part I and the imaginary part Q.
In the RF I-Q modulator 203, the sample is up-converted and sent to HPA 204. The HPA output is down-converted in RF I-Q Demodulator 214 and supplied to subtractor 212 through analog-digital converter (ADC) 213. The down-conversion allows us to measure the error, i.e., the difference between the input phase and magnitude of S(t), and the measured phase and magnitude at the HPA output. Obviously, delay unit 207 ensures that the input is compared to the correct output value by subtractor 212. The error signal output from the subtractor 212 is used to update the values currently stored in the LUT 208.
The input data signal is fed into the address calculator 205, which determines the address of the correction factor h in the LUT 208. This correction factor h modifies the input data signal. In the design shown in FIG. 2, power indexing is used to calculate the address.
The delay unit 207 delays the input sample S(t) by Δ and outputs the delayed sample S(t−Δ) to the subtractor 212. This delay compensates for the delay Δ of the predistorted signal traveling to the HPA 204 and then the HPA output making its way back to the feedback processing path. Thus the delay Δ is also because of the additional delays (latency) in the digital signal processing circuits such as multipliers and adders, and can exceed tens system clocks. The typical total traveling delay is 10-30 clocks, depending on the field programmable gate array (FPGA) used for the actual circuit and design properties.
In the simplest case, the LUT 208 must be updated every clock, i.e. the LUT 208 is updated every time when a new output sample y(t) is coming from ADC 213 and error signal err(t)=S(t−Δ)−y(t) is calculated. Such LUT updating strategy has a strong drawback. In fact, there is a significant problem with feedback loop dynamic performances and selection of the close loop gain.
As shown in FIG. 2, the HPA reaction for input stimulus S(t) is coming into the DPD circuit including adder 209, update unit 210, multiplier 211 and subtractor 212 after traveling delay. Typical DPD circuit determines the updated values of the correction factor h in the LUT 208 by comparing the feedback signal y(t) and the delayed input signal S(t−Δ). It is important that the feedback signal from HPA has to correspond to the stimulant input signal S(t−Δ).
The subtractor 212 outputs the error signal err(t) to the multiplier 211, the multiplier 211 multiplies the error signal err(t) by loop gain factor μ. Then the update unit 210 calculates difference Δh from the output of the multiplier 211 according to an adaptation algorithm. The adaptation algorithm is based on the least mean square (LMS) approach. The adder 209 adds the difference Δh to the current correction factor h and outputs updated correction factor h′ to the LUT 208. Delay unit 206 delays the read address for h by the delay Δ and supplies it to the LUT 208 as the write address for h′.
The main problem for DPD loop is that there is a relatively big delay between input signal sample S(t) and HPA reaction on this sample that comes through feedback. Typically this delay can exceed 30 master clocks of large-scale integration (LSI) or FPGA easily, or be even longer in some narrow-band systems. Such long response time causes that loop has a strong overshooting and in order to achieve operating stability the loop gain factor μ must be very low. Such a low gain causes a long time for LMS algorithm convergence.
Lets describe this problem in details with reference to FIGS. 3 and 4. Assume that input sample S(t) comes to the DPD input at time t1. The input sample is fed into the address calculator 205, which determines the address of the LUT 208 i.e. values for complex correction factor h. This sample S(t) is multiplied before the DAC 202 by the correction factor h drawn from the LUT 208. After correction the sample is up-converted in the RF I-Q modulator 203 and sent to the HPA 204. Some portion of RF signal from HPA output is down-converted to measure the error signal err(t) after the delay Δ.
Assume that the total traveling delay Δ equals 20 system clocks. The adaptation algorithm that is typically based on LMS approach, determines the value of the correction factor difference Δh≈err (t) by comparing the feedback signal y(t) at time t20 and the delayed input signal S(t−Δ). Thus, after correction at time t20 a new value for correction factor h′=h+Δh becomes available. This new value h′ is used for updating the LUT 208, i.e. h=h′. What is important about DPD is that the feedback signal y(t) as HPA reaction on the input signal S(t) comes with the traveling delay Δ.
The problem with DPD shown in FIG. 2 arises if the input signal samples S(t) at the consecutive times t1, t2, t3 and so on, are the same and use the same address in LUT 208 i.e. the samples use the same complex correction factor h, the overshooting will happen. Thus, after the initial correction h′=h+Δh at time t20, additional corrections will happen at times t21, t22 and so on. This is because LUT updating algorithm h′=h+Δh is still using the old (delayed) data y(t). Therefore, instead of a single correction of Δh for h, due to the traveling delay, additional corrections at times t21, t22 and so on will happen. Thus, the complex correction factor in this example at time t22 will equal to h′=h+3Δh instead of correct value h′=h+Δh, i.e. there is the three times overshooting. Such overshooting causes DPD instability and increases time required for convergence of an LMS algorithm.
Patent Documents 1 and 2 relate to a distortion compensator with a predistorter.    Patent Document 1: Japanese Patent Application Publication No. 2001-189685    Patent Document 2: Japanese Patent Application Publication No. 2005-020373    Non-patent Document 1: “Digital Predistortion Reference Design,” [online], [Searched Jun. 11, 2007], Internet <URL:http://www.altera.com/literature/an/an314.pdf>